The present invention relates to a semiconductor device and a method for fabricating the same and, more particularly, to a semiconductor device having a nitride-based compound semiconductor layer and a method for fabricating the same.
A Group III nitride-based compound semiconductor (hereinafter referred to as “Group III nitride semiconductor”) represented by gallium nitride (GaN) shows a breakdown field and a saturation electron velocity which are higher than those shown by silicon (Si) and gallium arsenide (GaAs). Therefore, a field effect transistor (hereinafter abbreviated as “FET”) using a group III nitride semiconductor is regarded as promising as a next-generation high-frequency device or high-power switching device and has been widely investigated.
In general, high-density trap states (surface states) exist at a surface of a group III nitride semiconductor so that carriers are trapped. Because of this, when a switching device, e.g., is produced by using a group III nitride semiconductor, the carriers trapped by the trap states cannot follow switching during high-speed switching. As a result, a phenomenon in which a drain current decreases, i.e., so-called current collapse occurs. As a method for suppressing the occurrence of the current collapse, the following solution has been known.
For example, as shown in FIG. 22, in Japanese Laid-Open Patent Publication No. 2002-359256, a GaN-based passivation layer 904 is provided on the upper surface of a carrier supply layer 903, and a passivation film 905 made of silicon nitride (SiN) covers the respective surface portions of the GaN-based passivation layer 904 located between a gate electrode 906 and a source electrode 907 and between the gate electrode 906 and a drain electrode 907. The arrangement allows a reduction in trap states at a group III nitride semiconductor. In FIG. 22, 901 denotes a substrate and 902 denotes a carrier transport layer.
On the other hand, it is disclosed in Japanese Laid-Open Patent Publication No. 2004-200248 that the upper surface of a Group III nitride semiconductor is covered with a silicon nitride film and a field plate electrode.
It is also disclosed in Japanese Laid-Open Patent Publication No. 2005-210105 that a recess is formed in the portion of a group III nitride semiconductor layer located under a gate electrode to provide a spike gate electrode, whereby frequency dispersion is suppressed.